Amphoteric p-type and n-type doping of group iii-vi semiconductors with group-iv atoms

ABSTRACT

Methods of forming a p-type IV-doped III-VI semiconductor are provided which comprise exposing a substrate to a vapor composition comprising a group III precursor comprising a group III element, a group VI precursor comprising a group VI element, and a group IV precursor comprising a group IV element, under conditions to form a p-type IV-doped III-VI semiconductor via metalorganic chemical vapor deposition (MOCVD) on the substrate. Embodiments make use of a flow ratio defined as a flow rate of the group VI precursor to a flow rate of the group III precursor wherein the flow ratio is below an inversion flow ratio value for the IV-doped III-VI semiconductor.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to U.S. Provisional PatentApplication No. 62/623,183 that was filed Jan. 29, 2018, the entirecontents of which are hereby incorporated by reference.

REFERENCE TO GOVERNMENT RIGHTS

This invention was made with government support under ECCS-1748339awarded by the National Science Foundation. The government has certainrights in the invention.

BACKGROUND

(Al,In,Ga)₂O₃ represents a newly developing III-VI family ofsemiconducting oxide materials. It holds great promise, but currentlysuffers from an inability to achieve effective p-type doping. Thematerial is typically doped using silicon (Group-IV) to substitute forgallium (or aluminum or indium) to achieve a n-type material. Magnesium(Group-II) has been used to substitute for the same gallium (or aluminumor indium) to achieve a p-type material. However, this requires theaddition of a separate magnesium source. In addition, magnesium exhibitsa large memory effect in metalorganic chemical vapor deposition (MOCVD)growth which means it is difficult to obtain p-n heterojunctions wherethe p-type material is grown first.

SUMMARY

Provided are methods of forming IV-doped III-VI semiconductors,including p-type III-VI semiconductors doped with Si. Also provided arethe IV-doped III-VI semiconductors and devices incorporating theIV-doped III-VI semiconductors.

In an aspect, methods of forming a p-type IV-doped III-VI semiconductorare provided which comprise exposing a substrate to a vapor compositioncomprising a group III precursor comprising a group III element, a groupVI precursor comprising a group VI element, and a group IV precursorcomprising a group IV element, under conditions to form a p-typeIV-doped III-VI semiconductor via metalorganic chemical vapor deposition(MOCVD) on the substrate. Embodiments make use of a flow ratio definedas a flow rate of the group VI precursor to a flow rate of the group IIIprecursor wherein the flow ratio is below an inversion flow ratio valuefor the IV-doped III-VI semiconductor.

In another aspect, a p-type IV-doped III-VI semiconductor is providedwhich comprises a group III element, a group VI element and a group IVelement.

Other principal features and advantages of the disclosure will becomeapparent to those skilled in the art upon review of the followingdrawings, the detailed description, and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Illustrative embodiments of the present disclosure will hereafter bedescribed with reference to the accompanying drawings.

FIG. 1A shows a plot of carrier concentration as a function of VI-IIIflow ratio for Ga₃O₂:Si formed according to an illustrative embodiment.FIG. 1B shows a plot of Hall mobility as a function of VI-III flow ratiofor Ga₃O₂:Si formed according to an illustrative embodiment.

FIG. 2A shows a cross-sectional view of a schematic of a field effecttransistor (FET) with a fin structure fabricated using p-type Ga₃O₂: Siaccording to an illustrative embodiment. FIG. 2B shows a perspectiveview of the fin-FET.

FIG. 3A is a plot of the I-V curve and FIG. 3B is a plot of the transfercharacteristics at V_(DS)=20 V of a p-type Ga₂O₃:Si 3 μm by 3 μm finarray fin-FET (shown in FIGS. 2A and 2B). The fin-FET shows an on/offratio of 10⁶ and a breakdown voltage of over 150 V.

FIG. 4A shows an XRD omega/2theta scan of ˜150 nm thick Ga₂O₃: Si grownusing a VI/III ratio of 150 (top), at a VI/III ratio of 100 (middle) andan XRD omega/2theta scan of a β-Ga₂O₃ substrate (TAMURA Corp) (bottom).FIG. 4B shows a TEM image of typical morphology of the ˜150 nm thickGa₂O₃:Si on sapphire. The inset shows SAED patterns obtained along the[5-10] zone axis at the κ-Ga₂O₃/Al₂O₃interface.

FIG. 5A shows the carrier concentration and resistivity of Ga₂O₃: Si onsapphire (0001) as a function of growth temperature at VI/III ratio of150 and FIG. 5B shows the same at a VI/III ratio of 100. FIG. 5C showsthe Hall mobility of Ga₂O₃:Si on sapphire (0001) as a function of growthtemperature at VI/III ratio of 100 and 150.

FIG. 6 shows I-V curves of ˜150 nm thick p-type Ga₂O₃:Si on sapphire(0001) from V_(GS)=−10 to 40 V and the inset is an optical microscopeimage of the fabricated device.

FIG. 7A show schematic illustrations of 2D p-type Ga₂O₃:Si channelmicrostrip array FETs with details of device scale FIG. 7B shows anoptical micrograph of the fabricated device.

FIG. 8A shows I-V curves from V_(GS)=−50 to 100 V. The inset is anoptical micrograph of the probing. FIG. 8B shows simulation data of I-Vcurves from V_(GS)=−40 to 40 V. FIG. 8C shows transfer characteristicsat V_(DS)=10 to 40 V.

FIG. 9A shows a schematic illustration of the 2D Ga₂O₃:Si channelmicrostrip array FETs. FIG. 9B shows a schematic illustration of threeportions of the Ga₂O₃ channel.

DETAILED DESCRIPTION

Provided are methods of forming IV-doped III-VI semiconductors,including p-type III-VI semiconductors doped with Si. Also provided arethe IV-doped III-VI semiconductors and devices incorporating theIV-doped III-VI semiconductors.

The present methods are based on the technique of metalorganic chemicalvapor deposition (MOCVD). As such, any reactor system suitable forcarrying out MOCVD may be used to carry out the methods. An embodimentof a method of forming an IV-doped III-VI semiconductor comprises a stepof exposing a substrate to a vapor composition comprising a group IIIprecursor comprising a group III element, a group VI precursorcomprising a group VI element, and a group IV precursor comprising agroup IV element. The exposure takes place under conditions sufficientto form a compound semiconductor from the group III, group VI, and groupIV precursors via MOCVD. That is, the group III, group VI, group IVprecursors adsorb to the surface of substrate where they react to formthe compound semiconductor, typically as a layer on the surface of thesubstrate. The method may include a predeposition step to form a wettinglayer on the substrate prior to exposure to the vapor composition. Thepredeposition step may comprise exposing the substrate to the group IIIprecursor (i.e., without the group VI precursor and without the group IVprecursor).

The group III precursors are metalorganic compounds comprising a groupIII element. In embodiments, the group III element is selected from Ga,Al, and In. A variety of group III precursors may be used, e.g.,trimethylgallium, trimethylaluminum, trimethylindium, triethylgallium,triethylaluminum, triethylindium, triisopropylgallium,triisopropylaluminum, triisopropylindium, triisobutylgallium, andtriisobutylaluminum. In embodiments, a single group III precursor isused, e.g., a gallium-containing group III precursor to provide aGa-group VI compound semiconductor. In embodiments, more than one groupIII precursor is used so as to facilitate alloying of the group IIIelements in the formation of the compound semiconductor. By ofillustration, a gallium-containing group III precursor, analuminum-containing group III precursor and an indium-containing groupIII precursor may be used to provide a GaAlIn-group VI compoundsemiconductor. In such a compound semiconductor, the ratios of Ga, Al,In may vary, depending upon the desired properties and application forthe semiconductor. As another illustration, a gallium-containing groupIII precursor and an indium-containing group III precursor may be usedto provide a Gain-group VI compound semiconductor. Again, in such acompound semiconductor, the ratios of Ga and In may vary.

The group VI precursors are compounds comprising a group VI element. Inembodiments, the group VI element is O. A variety of group VI precursorsmay be used, e.g., water, oxygen, N₂O, and ozone.

The group IV precursors are compounds comprising a group IV element. Inthe present methods, the group IV precursors are used as dopants, i.e.,to provide an IV-doped III-VI. In embodiments, the group IV element isSi. A variety of group IV precursors may be used, e.g., SiH₄,tetraethylorthosilicate, Si₂H₆, SiCl₄.

Because one or more of the group III, group VI, and group IV precursorsmay be provided in a carrier gas (e.g., N₂, Ar, H₂), the vaporcomposition may also comprise one or more such carrier gases.

By “conditions” as that term is used with respect to the presentmethods, refers to the growth temperature, the pressure of the vaporcomposition, the flow ratio of the group VI precursor to the group IIIprecursor, and the carrier gas. The present methods are based, at leastin part, on the finding that certain of these conditions may be adjustedto tune the doping type of the compound semiconductor from n-type top-type, even when using the same dopant, i.e., the same group IVprecursor. That is, certain of these conditions may be adjusted so thatthe group IV element of the group IV precursor substitutes for the groupVI element in the forming compound semiconductor to provide a p-typeIV-doped III-VI semiconductor or so that the group IV elementsubstitutes for the group III element to provide an n-type IV-dopedIII-VI semiconductor.

These findings are particularly surprising given the widely acceptedchallenges in the field for obtaining p-type III-VI semiconductors suchas p-type Ga₂O₃. Specifically, for p-type Ga₂O₃ thin films, shallowdonor level (due to oxygen vacancy) with low formation energy caninfluence the efficiency of doping and compensate for native acceptors.This requires high formation energy, which makes it difficult to growthe p-type material. See also Mastro et al., “Opportunities and FutureDirections for Ga₂O₃,” ECS Journal of Solid-State Science andTechnology, 6 (5) p. 356-359 (2017), which provides additional evidenceof these challenges.

By way of illustration, it has been found that the flow ratio of thegroup VI precursor to the group III precursor may be adjusted to provideboth an n-type IV-doped III-VI semiconductor (at certain flow ratios)and a p-type IV-doped III-VI semiconductor (at other flow ratios) evenwhen using the same group IV precursor. Similarly, an inversion flowratio value has been found, below which value a p-type IV-doped III-VIsemiconductor is formed and above which value a n-type IV-doped III-VIsemiconductor is formed even when using the same group IV precursor. Theinversion flow ratio value for a particular material system may bereferenced at a particular growth temperature, pressure, and carrier gasbeing used in the method.

These findings are demonstrated in the Examples below usingtrimethylgallium (group III precursor), water (group VI precursor) andsilane (group IV precursor) to provide both n-type Ga₃O₂:Si and p-typeGa₃O₂:Si simply by adjusting the flow ratio of the 0 precursor to the Gaprecursor. In other words, it has been found that Si acts as anamphoteric dopant for Ga₃O₂ via adjustments of the VI-III flow ratio.This vastly simplifies manufacturability of doped Ga₂O₃, therebyenabling many applications of this important material. Moreover, it hasbeen found that the inversion flow ratio value for this material systemis about 125. That is, for VI-III flow ratios below 125, the compoundsemiconductor formed is p-type (silicon substitutes for oxygen, takingup two extra electrons from the lattice, thus acting as a doubly ionizedacceptor to achieve very effective p-type doping). For VI-III flowratios above 125, the compound semiconductor formed is n-type (siliconsubstitutes for gallium). (See FIG. 1A.) This inversion flow ratio valueof 125 may be referenced, e.g., at a growth temperature of 1000° C., apressure of 50 mbar, and N₂ as the carrier gas.

FIGS. 5A-5C further support the findings described above. Moreover,these figures show the growth temperature does not changing the natureof doping, only the ratio of the flows of the group III and VIprecursors.

Thus, the present methods may comprise carrying out the step of exposureto the vapor composition under conditions (e.g., VI-III flow ratio)selected to achieve a desired doping type (either p-type or n-type) forthe IV-doped III-VI semiconductor being formed. Since both doping typesmay be achieved using the same group IV precursor, the methods mayfurther comprise forming a second IV-doped III-VI semiconductor havingthe opposite doping type to provide a p-n heterojunction. For example,the method can be used to form an n-type IV-doped III-VI semiconductoron a p-type IV-doped III-VI semiconductor or vice versa.

With reference back to the growth temperature and pressure describedabove, illustrative growth temperatures include those in the range offrom about 500° C. to about 1500° C., including from about 600° C. toabout 1000° C., or from about 700° C. to about 1000° C. Illustrativepressures include those in the range of from about 10 mbar to about 100mbar, including from about 50 mbar to about 150 mbar. A variety ofsubstrates may be used in the present methods, e.g., sapphire(a-sapphire, m-sapphire, c-sapphire), Al₂O₃, silicon (Si(111), Si(100)),native 13-Ga₂O₃, MgO, ZnO, etc.

The IV-doped III-VI semiconductors formed using the present methods arealso encompassed by the present disclosure. The IV-doped III-VIsemiconductors may be characterized by their carrier concentrations. Inembodiments, the IV-doped III-VI semiconductor is p-type having acarrier concentration in the range of from about 10¹⁵ cm⁻³ to about 10²⁰cm⁻³, from about 10¹⁶ cm⁻³ to about 10²⁰ cm′, from about 10¹⁷ cm⁻³ toabout 10²⁰ cm⁻³ or from about 10¹⁸ cm⁻³ to about 10²⁰ cm⁻³. Inembodiments, the IV-doped III-VI semiconductor is n-type having acarrier concentration in any of the ranges disclosed above. The IV-dopedIII-VI semiconductors may be characterized by their Hall mobility. Inembodiments, the Hall mobility may be in the range of from about 5 toabout 300 cm²/Vs, about 10 to about 300 cm²/Vs, or from about 5 to about150 cm²/Vs. Known techniques may be used to measure carrierconcentration and Hall mobility.

The IV-doped III-VI semiconductors may be characterized by the phase ofthe III-VI semiconductor. By way of illustration, for Ga₃O₂, the phaseof the material may be, e.g., or K.

Also encompassed by the present disclosure are p-n heterojunctionsformed from any of the disclosed p-type IV-doped III-VI semiconductorand another n-type semiconductor or from any of the disclosed p-typeIV-doped III-VI semiconductors and any of the disclosed n-type IV-dopedIII-VI semiconductors.

Devices incorporating the IV-doped III-VI semiconductors are alsoencompassed by the present disclosure. Illustrative devices includephotodetectors (including solar-blind UV photodetectors), field effecttransistors (including fin structured transistors see FIGS. 2A-2B and7A-7B), light emitting diodes and combinations thereof. Otherapplications include use of the IV-doped III-VI semiconductors in highvoltage direct current transmission lines, variable frequency drives andswitch mode power supplies.

Additional information regarding MOCVD, techniques for characterizingthe IV-doped III-VI semiconductors, and devices in which the IV-dopedIII-VI semiconductors may be incorporated may be found in the Appendix I(entire document), Appendix II (especially Section 2.2 and Section 4),and Appendix III (entire document) included in U.S. ProvisionalApplication No. 62/623,183, the entire contents of which are herebyincorporated by reference.

EXAMPLE Example 1

A commercial horizontal-flow MOCVD reactor (AIXTRON 200/4 RF) was usedto grow doped Ga₂O₃ thin films on c-plane sapphire (0001) at a growthtemperature of about 1000° C. using a conventional trimethylgallium(TMGa) bubbler and high purity deionized water loaded in a custom quartzbubbler as the gallium and oxygen precursors, respectively. Silane(SiH₄) was used as the silicon precursor. H₂ was used as the carriergas. First, TMGa was flowed for 1 minute to predeposit gallium on thesubstrate before introducing the water. Doped Ga₂O₃ thin films wereinvestigated using VI/III flow ratios in the range of from 100 to 150.

FIG. 1A shows the carrier concentration as a function of the III-VI flowratio. For VI-III flow ratios below ˜125 the as-grown material is p-type(silicon substitutes for oxygen). At an VI-III flow ratio of ˜125 aninversion takes place and the material becomes compensated. At an flowratio higher than ˜125 the material becomes n-type (silicon substitutesfor gallium). The only aspect of the growth that was changed was theVI-III flow ratio. In all cases, the growth temperature was 1000° C. andthe only variable changed was the ratio of the trimethylgallium andwater flow rate being introduced into the reaction chamber. The Hallmobility of the as-grown material as a function of the VI-III flow ratiois plotted in FIG. 1B.

In order to verify that the as-grown material is indeed p-type at lowVI-III flow ratios, a series of field effect transistors (FETs) with afin structure were fabricated using the p-type material (see FIGS. 2Aand 2B). An insulated gate consisting of ˜100 nm of silicon dioxide wasdeposited over the semiconductor material (i.e., p-type Ga₃O₂) andsource, drain, and gate contacts were deposited. The epitaxial layer ofGa₂O₃ was only ˜1.2 nm thick. Hall mobility measurements indicated thelayer was p-type with a carrier concentration of 3.423×10¹⁸ cm⁻³. Thesource-drain spacing was 20 μm and the gate was just 5 μm wide.

The fin-FET transistors were then experimentally characterized using anHP 4155C semiconductor parameter analyzer to measure the family ofcurves. The results are shown in FIGS. 3A and 3B. The measured resultsshow the excellent conductivity of the p-type layer achieved with thenovel doping technique used in this Example.

Example 2

Ga₂O₃ has emerged as a next generation semiconductor material for highpower electronic devices. This is in great part due to its highbreakdown electric field (˜8 MV/cm), which largely surpasses that ofcompeting materials systems such as SiC or GaN. Furthermore, theemergence of n-type doping capacity and single crystal Ga₂O₃ substrateshas allowed the development of various unipolar electronic devicesincluding metal oxide semiconductor field effect transistors (MOSFETs),Schottky diodes, metal semiconductor field effect transistors(MESFET).¹⁻³ The vast majority of this work has focused on homoepitaxialgrowth of monoclinic β-Ga₂O₃, which is the most stable of five commonpolymorphs (α, β γ, δ and ε). A major drawback of Ga₂O₃ till present,however, has been lack of a method to obtain p-type conduction. This isa key limitation for its adoption in a whole range of semiconductordevice applications. Moreover, the relatively low thermal conductivityof Ga₂O₃ and the problem of Ga₂O₃ substrate cost being two orders ofmagnitude higher than sapphire are both currently hindering the fullerdevelopment of Ga₂O₃ based power electronics.

κ-Ga₂O₃ (an orthorhombic polymorph which is normally considered to betransient) can be stabilized in heteroepitaxial growth on sapphire(0001) substrates by MOCVD.⁴ In this Example, it is shown that highlevels of shallow acceptor p-type conduction may be achieved in suchlayers using silicon impurity doping under Ga rich growth conditions. 2Dlayers of such p-type Ga₂O₃:Si are then processed into microstrip arrayring FETs using conventional photolithography. The operationalcharacteristics of the FETs proved to be consistent with p-typeconduction. This is the first demonstration of both shallow acceptordoping of Ga₂O₃ and a p-type Ga₂O₃ channel FET. A phenomenological modelcoherent with a p-type channel is also presented.

A commercial MOCVD reactor (AIXTRON 200/4 RF) was used to grow Ga₂O₃ onsapphire (0001) substrates at growth temperatures ranging from 730 to1000° C. Trimethylgallium (TMGa), high purity deionized water and SiH₄were adopted as the Ga, 0 and Si precursors, respectively. N₂ was usedas the carrier gas. Total pressure was 50 mbar. VI/III ratio was either100 (Ga-rich) or 150 (0-rich). The SiH₄ flow rate was fixed at 15 sccm.

As shown in FIG. 4A, XRD analysis was performed to analyze the phases ofthe grown ˜150 nm thick Ga₂O₃:Si with different VI/III ratio 100 and 150(top and middle). The XRD results show three peaks for each Ga₂O₃:Silayer. These three peaks were observed, similar to the results of theβ-Ga₂O₃ substrate (bottom). However the TEM analysis in FIG. 4B showedthe result of κ-phase with the space group of Pna²1.⁴ The κ-phase Ga₂O₃:Si was grown in the (002) direction and the 6 rotated domains wereobserved in the ˜150 nm thick Ga₂O₃:Si.

Electrical properties were measured using Van der Pauw Hallmeasurements. Ohmic contacts were obtained using a Ga/In eutectic. FIGS.5A and 5B show the results as a function of growth temperature for bothVI/III ratios. At a VI/III ratio of 150, Ga₂O₃:Si grown at 730° C. showsn-type characteristics. As growth temperature was increased from 730° C.to 1000° C., the carrier concentration decreased linearly to ˜4.4×10¹⁷cm⁻³. FIG. 5B shows that the lower VI/III ratio (100) consistently gavep-type characteristics. Assuming that the Si dopant acts as a shallowacceptor by substituting on the O-site of the Ga₂O₃, the VI/III ratio of100 growth condition would generate a higher density of oxygen vacancies(V_(O)) by virtue of the Ga-rich nature of the growth which lets the Sisubstitute more readily at the 0-sites. This assumption is consistentwith FIG. 2C which shows the Hall mobility of the Ga₂O₃:Si as a functionof growth temperature for VI/III ratios of 150 and 100. For a VI/IIIratio of 150, a (n-type) mobility near 50 cm²/Vs was observed for agrowth temperature of 1000° C. For a VI/III ratio of 100, a p-typemobility of ˜3.3 cm²/Vs was observed. This demonstrates Si is acting asan amphoteric dopant in κ-Ga₂O₃. Si impurity doping is generallyincorporated so as to substitute for Ga where it acts as a shallow donorso as to create heavily doped n-type Ga₂O₃. But as the density of V_(O)increases under Ga-rich growth conditions, the above results suggestthat Si can act as a shallow acceptor by substituting on the O-sites inκ-Ga₂O₃, and thus promote a transformation to predominantly p-typeconduction. These p-type results were confirmed via multiple independentmeasurements.

Ring type FETs were fabricated and evaluated for the characteristics ofthe FET device of ˜150 nm thick p-type Ga₂O₃:Si with VI/III ratio of100. FIG. 6 shows the I-V curves. It is observed that the drain currentdecreases with increasing gate voltage. However, it was not possible toachieve pinch-off due to the gate electrode burning at gate voltageshigher than 50 V. To avoid this issue the channel thickness was reducedto ˜1.2 nm and the ring pattern FETs were patterned with microstrips.Ga₂O₃:Si channel layers were grown at 1000° C. with a VI/III ratio of100. The channel thickness was estimated to be ˜1.2±0.5 nm based oninterferometric growth rate calibration and AFM step-edge profilometry.Hall measurements confirmed the p-type nature of the layers with aresistivity of ˜0.007 Ω·cm, a carrier concentration of ˜1.7×10²⁰ cm′ anda mobility of ˜5.7 cm²/V·s.

Standard photolithography and lift-off were employed to deposit sourceand drain metal contacts. Before their deposition, 3 μm×3 μm microstrippatterns were formed by electron cyclotron resonance-reactive ionetching (ECR-RIE) with CF₄ for 5 minutes. The metal contacts were Ti (20nm)/Au (150 nm) deposited by e-beam evaporation. SiO₂ of 100 nm thickgate dielectric material was formed by plasma-enhanced chemical vapordeposition (PECVD). After dielectric and passivation film deposition,the gate metal contact was formed with Pt(20 nm)/Ti(20 nm)/Au(150 nm) onthe SiO₂ film. The gate length, and the spacing between the source/drainand the inside source circular pad were 15, 20 and 100 μm, respectively.FIG. 7A shows schematic illustrations of the device with top- andcross-sectional views illustrating the device scale. FIG. 7B shows anoptical microscope image of the fabricated device.

Next, the FETs were fabricated and tested using a semiconductorparameter analyzer and probe station. FIG. 8A shows the DC source-draincurrent versus source-drain voltage (I_(DS)−V_(DS)) outputcharacteristics for the depletion-mode FETs measured by increasinggate-source voltage (V_(GS)) stepwise from −50 to 100 V. The maximumI_(DS) was 2.19 mA and it was effectively modulated by V_(GS) from −50to 100 V, which is consistent with a p-type channel. Because of theheavy p-doping, the 2D microstrip channel is normally-on, and thechannel off-state was observed for a gate bias of 50 V (I_(DS)=0.1 pA atV_(DS) of 40 V). In addition, because of the high sheet resistance, evenwith a drain voltage as high as 40 V, the voltage drop in the FETchannel is still lower than |V_(G)−V_(T)|, which is the condition forcurrent saturation in long channel FETs. So the I_(DS)−V_(DS)characteristics remain linear. FIG. 8B displays a similar set of curvesobtained from the simulation. It can be seen that the theoretical modelis consistent with the experimental data in showing an output resistanceincrease with positive gate voltage, and I_(DS) bunching with littlevariation of the output resistance for V_(GS)<0. This is also consistentwith a p-type channel. FIG. 8C shows transfer characteristics at V_(DS)of 10 to 40 V in a logarithmic scale. The device achieved an on/offratio of ˜10⁸ by minimizing the thickness and width of the channel. Aplot of the gate current as a function of drain-source voltage (notshown) showed that I_(G) increases above a V_(GS) of 50 V because of agate leakage current. It is expected that the on/off ratio can befurther improved through optimization of the dielectric layer.

A phenomenological model was developed based on the device configurationdisplayed in FIGS. 7A-7B. FIGS. 9A-9B show the schematic of the modeldevice that consists of a linear array of δ=3 μm wide micro-stripsseparated from each other by δ=3 μm. They are covered by a disk-shapedsource contact of 200 μm in diameter, and separated from a square shapeddrain by a 30 μm wide circular channel. So, in each quadrant, thechannel length, L_(i), varies between a minimum value when it isperpendicular to the disk and a maximum value when it is tangential tothe disk. The position of the i^(th) microstrip is identified by itsdistance, d_(i), from the center of the source disk.

At V_(G)=0 V, the channel is uniform and the current between source anddrain in the i^(th) micro-strip channel is given by

I _(i) =ep _(S) δv _(i)  (1)

where e is the electron charge (C), p_(S) is the 2D hole concentration(carriers/cm²), δ the wire width (cm) and υ_(i) is the hole velocity inthe i^(th) channel (cm/s). In the absence of saturation velocity (longchannel-low mobility),

$\begin{matrix}{v_{i} = \frac{\mu \; V_{DS}}{L_{i}}} & (2)\end{matrix}$

where μ is the hole mobility (cm²/Vs) and L_(i) is the channel length(cm).

If d_(i)=2iδ with 0<i<N, Equ. 1 becomes for top and bottom rightquadrants

I _(right)=2Σ_(i=0) ^(N) I _(i) =ep _(S) μV _(DS)Σ_(i=0) ^(N)1/[√{squareroot over ((N+5)² −i ²)}−√{square root over (N ² −i ²)}]=2.84ep _(S) ηV_(DS)  (3)

Because of the relatively big gate pad on the left side of the source,channel lengths are longer for a sizeable portion of theFIN-microstrips, so it is estimated that the total current should bemultiplied by a factor η˜1.8-1.9<2. Finally,

I=I _(Right) +I _(Left) =ηI _(Right)  (4)

At V_(G)≠0, the channel is made of three portions with differentconductances (FIG. 9B). By neglecting the contact resistance, for eachchannel,

$\begin{matrix}{{{I_{i}( V_{G} )} = {\frac{V_{DS}}{\frac{1}{G_{1}^{i}} + \frac{1}{G_{2}^{i}} + \frac{1}{G_{3}^{i}}}\mspace{14mu} {with}}}\mspace{14mu} {G_{1,3}^{i} = {{\frac{{{ep}_{S}( {V_{G} = 0} )}{\delta\mu}}{L_{1,3}^{i}}\mspace{31mu} G_{2}^{i}} = \frac{{{ep}_{S}( {V_{G} \neq 0} )}{\delta\mu}}{L_{2}^{i}}}}} & (5)\end{matrix}$

If

${{p_{S}( {V_{G} \neq 0} )} = {{p_{S}( {V_{G} = 0} )}{\exp ( {- \frac{eVc}{kT}} )}}},$

where V_(C)(V_(G)) is the channel potential induced by the gate bias,the expression for the current reads

I _(i)(V _(G))=ep _(S)(V _(G)=0)δμV _(DS)/(L ₁ ^(i) +L ₂ ^(i) exp(eV_(C) /kT)+L ₃ ^(i))  (6)

or after summation over all channels,

$\begin{matrix}{{I( V_{G} )} = \frac{2{I( {V_{G} = 0} )}}{1 + {\exp ( \frac{eVc}{kT} )}}} & (7)\end{matrix}$

This equation shows that for V_(C)<0 (V_(G)<O) the drain currentdecreases, whereas for V_(C)>0 (V_(G)>0) the drain current increases inagreement with the experimental data. This is consistent with thechannel being p-type. In quantitative terms, it shows that currentdecreases by several orders of magnitude under positive V_(G) comparedto a limiting increase by a factor 2 under negative V_(G). Thisasymmetry in the variation of the I-V characteristics for V_(G)<0 andV_(G)>0 is also consistent with the experimental data.

From the Poisson equation, one can derive an expression of V_(C) forintermediate gate bias:

$\begin{matrix}{{V_{C}(y)} = \frac{V_{G}\lambda_{D}{\exp ( {- \frac{y - D}{\lambda_{D}}} )}}{D + \lambda_{D}}} & (8)\end{matrix}$

where D is the thickness of the SiO₂ barrier, y is the verticalcoordinate inside the Ga₂O₃ layer, and λ_(D) is the Debye length in theGa₂O₃ layer fitted to reproduce the experimental I-V characteristics.FIG. 8B displays simulation data of I-V curves from V_(GS)=−40 to 40 V,for which a channel mobility μ=23 cm²/Vs and hole concentrationp_(S)=2.35×10¹²/cm² was used.

In conclusion, κ-Ga₂O₃:Si layers grown on sapphire (0001) substrates byMOCVD showed consistent p-type Hall signal for layers grown with lowerVI/III ratios during growth. Room temperature mobilities were up to 7cm²/Vs, resistivities were as low as 0.007 Ω·cm and carrierconcentrations were up to ˜10²⁰ cm⁻³ for thinner layers. Ring mesa FETswere fabricated based on ˜1.2 nm thick p-Ga₂O₃:Si channels formed into anumber of 3 μm wide microstrips. The devices achieved a maximum draincurrent density of 2.19 mA and an on/off ratio of ˜10⁸ and showedcharacteristics consistent with a p-type conduction in the channel.

The p-type Ga₂O₃ demonstrated in this Example represents a significantadvance in the state of the art, which may herald the fabrication of arange of p-n junction based devices. These may be smaller/thinner andbring both cost (more devices/wafer and less growth time) and operatingspeed advantages (due to miniaturisation) than current isotype FETs.Moreover the demonstration of the first functioning devices based onscaling down to 2D device channels in Ga₂O₃ based FETs opens up theperspective of faster devices and improved heat evacuation.

REFERENCES FOR EXAMPLE 2

-   ¹M. Higashiwaki, K. Sasaki, T. Kamimura, M. Hoi Wong, D.    Krishnamurthy, A. Kuramata, T. Masui, and S. Yamakoshi, Appl. Phys.    Lett. 103, 123511 (2013).-   ² K. Sasaki, M. Higashiwaki, A. Kuramata, T. Masui, and S.    Yamakoshi, J. Cryst. Growth 378, 591 (2013).-   ³ K. Sasaki, DaikiWakimoto, Q. T. Thieu, Y. Koishikawa, A.    Kuramata, M. Higashiwaki, and S. Yamakoshi, IEEE Electron Device    Lett. 38, 783 (2017).-   ⁴ M. Razeghi, J.-H. Park, R. McClintockl, D. Pavlidis, F. H.    Teherani, D. J. Rogers, B. A. Magill, G. A. Khodaparast, Y. Xu, J.    Wu, and V. P. Dravid, Proc. SPIE 10533, 105330R (2018).-   ⁵ A. Munoz-Yague and S. Baceiredo, J. Electrochem. Soc. 129, 2108    (1982).-   ⁶ I. TERAMOTO, J. Phys. Chem. Solids 33, 2089 (1972).-   ⁷ H. P. Meier, R. F. Broom, P. W. Epperlein, E. van Giesen, C.    Harder, and H. Jackel, J. Vac. Sci. Technol. B 6, 692 (1988).-   ⁸ K. Agawa, K. Hirakawa, N. Sakamoto, Y. Hashimoto, and T. Ikoma,    Appl. Phys. Lett. 65, 1171 (1994).-   ⁹ A. A. Quivy, A. L. Sperandio, E. C. F. Silva, and J. R. Leite, J.    Cryst. Growth 206, 171 (1999).-   ¹⁰ T. Oishi, Y. Koga, K. Harada, and M. Kasu, Appl. Phys. Express 8,    031101 (2015).-   ¹¹ M. Baldini, M. Albrecht, A. Fiedler, K. Irmscher, R. Schewski,    and G. Wagner, ECS J. Solid State Sci. Technol. 6, Q3040 (2017).

The word “illustrative” is used herein to mean serving as an example,instance, or illustration. Any aspect or design described herein as“illustrative” is not necessarily to be construed as preferred oradvantageous over other aspects or designs. Further, for the purposes ofthis disclosure and unless otherwise specified, “a” or “an” means “oneor more.”

The foregoing description of illustrative embodiments of the disclosurehas been presented for purposes of illustration and of description. Itis not intended to be exhaustive or to limit the disclosure to theprecise form disclosed, and modifications and variations are possible inlight of the above teachings or may be acquired from practice of thedisclosure. The embodiments were chosen and described in order toexplain the principles of the disclosure and as practical applicationsof the disclosure to enable one skilled in the art to utilize thedisclosure in various embodiments and with various modifications assuited to the particular use contemplated. It is intended that the scopeof the disclosure be defined by the claims appended hereto and theirequivalents.

What is claimed is:
 1. A method of forming a p-type IV-doped III-VIsemiconductor, the method comprising: exposing a substrate to a vaporcomposition comprising a group III precursor comprising a group IIIelement, a group VI precursor comprising a group VI element, and a groupIV precursor comprising a group IV element, under conditions to form ap-type IV-doped III-VI semiconductor via metalorganic chemical vapordeposition (MOCVD) on the substrate.
 2. The method of claim 1, whereinthe conditions comprise use of a flow ratio defined as a flow rate ofthe group VI precursor to a flow rate of the group III precursor and theflow ratio is below an inversion flow ratio value for the IV-dopedIII-VI semiconductor so as to provide the p-type IV-doped III-VIsemiconductor.
 3. The method of claim 1, further comprising exposing thesubstrate to the vapor composition under conditions to form an n-typeIV-doped III-VI semiconductor via MOCVD from the vapor composition. 4.The method of claim 3, wherein the n-type IV-doped III-VI semiconductoris in contact with the p-type IV-doped III-VI semiconductor, therebyforming a p-n heterojunction.
 5. The method of claim 3, wherein theconditions comprise use of a flow ratio defined as a flow rate of thegroup VI precursor to a flow rate of the group III precursor and theflow ratio is above an inversion flow ratio value for the IV-dopedIII-VI semiconductor so as to provide the n-type IV-doped III-VIsemiconductor.
 6. The method of claim 1, wherein the conditions compriseuse of a first flow ratio defined as a flow rate of the group VIprecursor to a flow rate of the group III precursor to provide thep-type IV-doped III-VI semiconductor; wherein the method furthercomprises exposing the substrate to the vapor composition underconditions to form an n-type IV-doped III-VI semiconductor via MOCVDfrom the vapor composition, wherein the conditions comprise use of asecond, different flow ratio to provide the n-type IV-doped III-VIsemiconductor.
 7. The method of claim 6, wherein the n-type IV-dopedIII-VI semiconductor is in contact with the p-type IV-doped III-VIsemiconductor, thereby forming a p-n heterojunction.
 8. The method ofclaim 1, wherein the group III precursors are selected from aGa-containing group III precursor, an Al-containing group III precursor,an In-containing group III precursor and combinations thereof.
 9. Themethod of claim 1, wherein the group III precursor is a Ga-containinggroup III precursor.
 10. The method of claim 1, wherein the group VIprecursor comprises O.
 11. The method of claim 1, wherein the group IVprecursor comprises Si.
 12. The method of claim 1, wherein the carriergas comprises N₂, H₂, Ar, or combinations thereof.
 13. The method ofclaim 1, wherein the group III precursors are selected from aGa-containing group III precursor, an Al-containing group III precursor,an In-containing group III precursor and combinations thereof; whereinthe group VI precursor comprises O; and wherein the group IV precursorcomprises Si.
 14. The method of claim 13, wherein the p-type IV-dopedIII-VI semiconductor formed is p-type Si-doped Ga₂O₃.
 15. The method ofclaim 13, wherein the p-type IV-doped III-VI semiconductor formed isp-type Si-doped (Ga,In)₂O₃.
 16. The method of claim 13, wherein thecarrier gas comprises N₂, H₂, Ar, or combinations thereof.
 17. A p-typeIV-doped III-VI semiconductor comprising a group III element, a group VIelement and a group IV element.
 18. A p-n heterojunction comprising alayer of an n-type semiconductor in contact with the p-type IV-dopedIII-VI semiconductor of claim
 17. 19. The p-n heterojunction of claim18, wherein the n-type semiconductor is an n-type IV-doped III-VIsemiconductor comprising the group III element, the group VI element andthe group IV element.
 20. A device comprising the p-type IV-doped III-VIsemiconductor of claim 17 and another material layer in contact with thep-type IV-doped III-VI semiconductor.